As SOCs (system-on-a-chip) become more highly integrated with millions of devices being packed into a single SOC, power consumption is a critical design consideration due to the increasing gap between the energy required by portable computation/communication devices and the energy supplied by the battery. Traditionally, in a CMOS device, power consumption is caused primarily from the switching of logic states. In particular, the switching power is expressed as:Pswitch=α0→1·fCLK(Cload−Vdd2)where α0→1 is the average number of times in a clock cycle that a switch from a logic level “0” to “1” occurs, fCLK is the clock frequency, Cload is the load capacitance and where Vdd is the supply voltage. The equation clearly shows the supply voltage affects power dissipation in a quadratic order.
Single-cycle SRAM caches that are employed for fast, low cost wireless DSP applications (such as 3G cell phones) impose stringent design constraints on active power. With increases in the spread of Vt (threshold voltage) fluctuations that exist in cell and sense amplifier transistors, delay variability of the bit path increases dramatically at low operating voltages, requiring larger margins for evaluate periods of the SRAM cell and sense amplifiers. As a result, the bitpath power increases, which dominates SRAM active power.
In a conventional SRAM, control pulses are driven across a memory array to implement specific functions such as precharging/equalizing bitlines or enabling sense amplifiers and write buffers. Typically, these control pulses are gated-off by block select signals coming off a decode network that identify a specific set of memory blocks from which data is being read, or to which data is being written. This conventional method is disadvantageous in that skew is developed between edges of the control pulses that enable the wordline (WL) (coming from the decode network) and the pulses that precharge/equalize bitlines and that enable sense amplifiers and write buffers. Consequently, such skew requires generation of control pulses have larger pulse widths, to thereby develop more signal to accommodate process, random and environment variations. However, larger pulse widths directly results in higher active power and lower performance.
Various techniques to match the clock path with the bitpath using dummy bit lines BLs to minimize skew have been proposed, but such techniques do not address the random sources of variation such as dopant fluctuations or line edge roughness (LER) from which the skew between pulses along the clock and bitpath become significant. In addition, these techniques not only require significantly more design effort, but only address the skew development between the WL and the sense amplifier enabling edges.
Therefore, it would be highly desirable to develop circuits and methods for controlling memory access operations in a CMOS-based SRAM, for example, which would enable efficient synchronization between control pulses for controlling read/write circuitry, while minimizing the power dissipation associated with such control.